Complimentary metal oxide semiconductor (CMOS) structures are the core active elements of modern electronics. Undoubtedly, the major material enabling features of Si CMOS are the superb quality of the native silicon dioxide (SiO2), Si/SiO2 interface and high crystalline perfection of the Si substrates. The field effect transistor (FET) implemented as CMOS is scalable. That is, speed and complexity improves with decreasing device feature sizes. This concept makes CMOS architecture a powerful methodology. Deep submicron room-temperature bulk Si CMOS is presently the main technology used for ultra large scale integrated circuits (ULSICs).
Because silicon is the major semiconductor material used in the semiconductor industry, silicon dioxide (SiO2) is the major insulating material used in the gate insulating layer. Silicon dioxide is a natural material that can be easily grown thermally through a steam process. Also, the silicon dioxide forms a bond with the crystalline silicon active layer that determines most of the characteristics of the FET so that it is very difficult to change the insulating material of the gate insulating layer without having deleterious effects on the FET.
However, several problems do arise from the use of silicon dioxide as the gate insulating layer. Continued scaling of current CMOS architecture is reaching the limits of the material properties of both the SiO2 gate dielectric and bulk Si substrate. As the length and thickness of the gate insulating layer is made smaller, defects and other materials in the gate insulating layer greatly affect the reliability, lifetime, and operating characteristics of the FET. Thus, any impurities in the gate stack, such as the dopant material used in doping of layers to produce the desired Schottky electrical contact of the gate, can cause serious problems. The impurities or doping materials are a problem because they migrate into the gate insulating layer and sometimes even into the active layer to produce defects and changes in operating characteristics.
Another problem with a silicon dioxide insulating layer on a layer of crystalline silicon is the strain produced by stress introduced at the junction by the lattice mismatch between the silicon and the thermally formed silicon dioxide. The lattice mismatch results in a relatively high compressive stress at the junction between the two materials. In many instances this high stress can result in dislocations, crystalline defects, and even fractures in the active layer. To provide an unstressed or unstrained active layer, the thickness of the silicon dioxide layer must be severely limited to a thickness at which the stress substantially disappears. That is, in each atomic layer of the silicon dioxide a small amount of the stress can be removed by lattice matching until, ultimately, all stress is removed (stress distribution). However, the result is a layer of silicon dioxide that is too thick to be of use in many applications, such as gate oxides in very small field effect transistors and the like.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved method of fabricating gate structures for field effect transistors and the like.
Another object of the invention is to provide new and improved gate structures for field effect transistors and the like.
Another object of the invention is to provide a new and improved method of fabricating gate structures to improve manufacturing consistency and consistent semiconductor component characteristics and to simplify the fabrication process.
A further object of the present invention is to provide gate structures for semiconductor components that improve the reliability, lifetime, and operating characteristics of the semiconductor components.
A further object of the present invention is to provide FET gate structures for semiconductor components that reduces the impurity diffusion from the gate contact layer into the gate oxide and or active layer.